mux8.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;

entity mux8 is
  generic (width : positive;
      	    Tpd : Time := unit_delay);
  port (i0, i1, i2, i3, i4, i5, i6, i7 : in bit_vector(width-1 downto 0);
      	y : out bit_vector(width-1 downto 0);
	sel : in bit_vector(2 downto 0));
end mux8;

architecture behaviour of mux8 is
	
begin
  
  with sel select
    y <=  i0 after Tpd when "000",
      	  i1 after Tpd when "001",
	  i2 after Tpd when "010",
          i3 after Tpd when "011",
	  i4 after Tpd when "100",
 	  i5 after Tpd when "101",
	  i6 after Tpd when "110",
	  i7 after Tpd when "111";
end behaviour;