latch_buffer_32.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: latch_buffer_32.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/05/24 16:57:44 $
--

use work.dp32_types.all;

entity latch_buffer_32 is
  generic (Tpd : Time := unit_delay);
  port (d : in bit_32;
      	q : out bus_bit_32 bus;
	latch_en : in bit;
	out_en : in bit);
end latch_buffer_32;

architecture behaviour of latch_buffer_32 is

begin 

  process (d, latch_en, out_en)
    variable latched_value : bit_32;
  begin
    if latch_en = '1' then
      latched_value := d;
    end if;
    if out_en = '1' then
      q <= latched_value after Tpd;
    else
      q <= null after Tpd;
    end if;
  end process;

end behaviour;