mux4.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;

entity mux4 is
  generic (width : positive;
      	    Tpd : Time := unit_delay);
  port (i0, i1, i2, i3: in bit_vector(width-1 downto 0);
      	y : out bit_vector(width-1 downto 0);
	sel : in bit_vector(1 downto 0));
end mux4;

architecture behaviour of mux4 is
	
begin
   with sel select
    y <=  i0 after Tpd when "00",
      	  i1 after Tpd when "01",
	  i2 after Tpd when "10",
          i3 after Tpd when "11";
end behaviour;