pc_reg.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: PC_reg.vhd,v $
-- $Revision: 1.2 $
-- $Author: petera $
-- $Date: 90/05/29 10:13:02 $
--

use work.dp32_types.all;

entity PC_reg is
  generic (Tpd : Time := unit_delay);
  port (d : in bit_32;
	q : out bus_bit_32 bus;
	latch_en : in bit;
	out_en : in bit;
	reset : in bit);
end PC_reg;

architecture behaviour of PC_reg is
  
begin

  process (d, latch_en, out_en, reset)
    variable master_PC, slave_PC : bit_32;
  begin
    if reset = '1' then
      slave_PC := X"0000_0000";
    elsif latch_en = '1' then
      master_PC := d;
    else
      slave_PC := master_PC;
    end if;
    if out_en = '1' then
      q <= slave_PC after Tpd;
    else
      q <= null after Tpd;
    end if;
  end process;

end behaviour;