xor.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;

entity g_xor is
    generic(width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0));  
end g_xor;

architecture behaviour of g_xor is
begin

y<=a xor b;
end behaviour;



entity g_xor_b is
    port(a,b : in bit;
         y : out bit);
end g_xor_b;

architecture behaviour of g_xor_b is
begin

y<=a xor b;
end behaviour;