1(3).txt

3-8译码器,BCD码转换10进制,计数器

Library IEEE;
Use IEEE.Std_Logic_1164.All;
Entity muxdecoder Is
Port(a:In std_Logic_Vector(3 downto 0);
     b:In Std_Logic_Vector(3 downto 0);
     clk:In Std_Logic;
     y:out Std_Logic_Vector(6 downto 0);
     sel:Out std_Logic_Vector(2 downto 0));
End Entity muxdecoder;
Architecture behaviour Of muxdecoder Is 
Begin 
Process(clk,a,b)
 Begin 
  If clk='1' Then 
  sel<="001";
  Case a Is
   When "0000"=>y<="0111111";
   When "0001"=>y<="0000110";
   When "0010"=>y<="1011011";
   When "0011"=>y<="1001111";
   When "0100"=>y<="1100110";
   When "0101"=>y<="1101101";
   When "0110"=>y<="1111101";
   When "0111"=>y<="0000111";
   When "1000"=>y<="1111111";
   When "1001"=>y<="1101111";
   When "1010"=>y<="1110111";
   When Others=>NULL;
 End Case;
Else 
 sel<="010";
Case B Is
   When "0000"=>y<="0111111";

   When "0001"=>y<="0000110";
   When "0010"=>y<="1011011";
   When "0011"=>y<="1001111";
   When "0100"=>y<="1100110";
   When "0101"=>y<="1101101";
   When "0110"=>y<="1111101";
   When "0111"=>y<="0000111";
   When "1000"=>y<="1111111";
   When "1001"=>y<="1101111";
   When "1010"=>y<="1110111";
   When Others=>NULL;
End Case;
End If;
END pROCESS;
End behaviour;