vhdl code1.bak

来自「d flip flop t flip flop counter mux usin」· BAK 代码 · 共 22 行

-- This is the VHDL code for the counter example from _The VHDL
-- Cookbook_ by Peter Ashenden.  The propogation delay has been removed.

entity count2 is
  port (clock : in bit; q1, q0 : out bit);
end count2;


architecture behaviour of count2 is
begin
  count_up: process (clock)
    variable count_value : natural := 0;
  begin
    if (clock = '1') then
      count_value := (count_value + 1) mod 4;
      q0 <= bit'val(count_value mod 2);
      q1 <= bit'val(count_value / 2);
    end if;
  end process count_up;
end behaviour;