代码搜索：Annotation

找到约 6,069 项符合「Annotation」的源代码

代码结果 6,069
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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ant code_wave.ant

-- C:\XILINX\BIN\MYCPU16 -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Thu Nov 15 13:40:12 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIB
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www.eeworm.com/read/314805/13558804

ant alu_wave.ant

-- C:\XILINX\BIN\MYCPU16 -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Thu Nov 15 13:33:14 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEE
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ant wave.ant

-- C:\XILINX\BIN\MYCPU16 -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Thu Nov 15 13:56:25 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIB
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www.eeworm.com/read/314805/13558926

ant visit_memory_wave.ant

-- C:\XILINX\BIN\MYCPU16 -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Thu Nov 15 13:55:43 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIB
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www.eeworm.com/read/213395/15135697

ant wave.ant

// E:\FPGA\CLKGEN // Verilog Annotation Test Bench created by // HDL Bencher 6.1i // Fri May 18 22:21:23 2007 `timescale 1ns/1ns module wave; reg clk; reg reset; wire clk1; wire clk2;
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www.eeworm.com/read/210233/15203351

ant lock_tw.ant

-- E:\VHDL\WAITPAST\QIANGDAQI4REN -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Sat Mar 24 14:41:25 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL
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www.eeworm.com/read/210233/15203551

ant qd_tw.ant

-- E:\VHDL\WAITPAST\QIANGDAQI4REN -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Sat Mar 24 14:51:18 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; US
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www.eeworm.com/read/210231/15203782

ant ch_tw.ant

-- E:\VHDL\WAITPAST\DIG_CLK -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Wed Apr 18 11:01:14 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE
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www.eeworm.com/read/210231/15203786

ant m59.ant

-- E:\VHDL\WAITPAST\DIG_CLK -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Wed Apr 18 11:26:00 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE
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www.eeworm.com/read/210231/15203887

ant lcd_tw.ant

-- E:\VHDL\PAST\DIG_CLK -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Tue Apr 17 20:33:46 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE
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