visit_memory_wave.ant

16位cpu设计VHDL源码

-- C:\XILINX\BIN\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:55:43 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY visit_memory_wave IS
END visit_memory_wave;

ARCHITECTURE testbench_arch OF visit_memory_wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\xilinx\bin\mycpu16\visit_memory_wave.ano";
	COMPONENT visit_memory
		PORT (
			PCload : In  std_logic;
			PCout : In  std_logic_vector (15 DOWNTO 0);
			IRnew : Out  std_logic_vector (15 DOWNTO 0);
			clk : In  std_logic;
			nMRD : In  std_logic;
			nMWR : In  std_logic;
			Addr : In  std_logic_vector (15 DOWNTO 0);
			ALUout : In  std_logic_vector (7 DOWNTO 0);
			data : Out  std_logic_vector (7 DOWNTO 0);
			Dbus : InOut  std_logic_vector (15 DOWNTO 0);
			Abus : Out  std_logic_vector (15 DOWNTO 0);
			nWR : Out  std_logic;
			nRD : Out  std_logic;
			nBLE : Out  std_logic;
			nBHE : Out  std_logic;
			nMREQ : Out  std_logic
		);
	END COMPONENT;

	SIGNAL PCload : std_logic;
	SIGNAL PCout : std_logic_vector (15 DOWNTO 0);
	SIGNAL IRnew : std_logic_vector (15 DOWNTO 0);
	SIGNAL clk : std_logic;
	SIGNAL nMRD : std_logic;
	SIGNAL nMWR : std_logic;
	SIGNAL Addr : std_logic_vector (15 DOWNTO 0);
	SIGNAL ALUout : std_logic_vector (7 DOWNTO 0);
	SIGNAL data : std_logic_vector (7 DOWNTO 0);
	SIGNAL Dbus : std_logic_vector (15 DOWNTO 0);
	SIGNAL Abus : std_logic_vector (15 DOWNTO 0);
	SIGNAL nWR : std_logic;
	SIGNAL nRD : std_logic;
	SIGNAL nBLE : std_logic;
	SIGNAL nBHE : std_logic;
	SIGNAL nMREQ : std_logic;

BEGIN
	UUT : visit_memory
	PORT MAP (
		PCload => PCload,
		PCout => PCout,
		IRnew => IRnew,
		clk => clk,
		nMRD => nMRD,
		nMWR => nMWR,
		Addr => Addr,
		ALUout => ALUout,
		data => data,
		Dbus => Dbus,
		Abus => Abus,
		nWR => nWR,
		nRD => nRD,
		nBLE => nBLE,
		nBHE => nBHE,
		nMREQ => nMREQ
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_IRnew(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",IRnew,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, IRnew);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_data(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",data,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_Abus(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Abus,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Abus);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nWR(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nWR,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nWR);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nRD(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nRD,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nRD);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nBLE(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nBLE,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nBLE);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nBHE(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nBHE,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nBHE);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nMREQ(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nMREQ,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nMREQ);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_Dbus(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Dbus,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Dbus);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_IRnew(TX_TIME);
		ANNOTATE_data(TX_TIME);
		ANNOTATE_Abus(TX_TIME);
		ANNOTATE_nWR(TX_TIME);
		ANNOTATE_nRD(TX_TIME);
		ANNOTATE_nBLE(TX_TIME);
		ANNOTATE_nBHE(TX_TIME);
		ANNOTATE_nMREQ(TX_TIME);
		ANNOTATE_Dbus(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		PCload <= transport '0';
		PCout <= transport std_logic_vector'("0000000000000000"); --0
		nMRD <= transport '1';
		nMWR <= transport '1';
		Addr <= transport std_logic_vector'("0000000000000000"); --0
		ALUout <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		PCload <= transport '1';
		Dbus <= transport std_logic_vector'("0101000010101011"); --50AB
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		PCload <= transport '0';
		Dbus <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		PCload <= transport '1';
		PCout <= transport std_logic_vector'("0000000000000001"); --1
		Dbus <= transport std_logic_vector'("0100000100000000"); --4100
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		PCload <= transport '0';
		PCout <= transport std_logic_vector'("0000000000000000"); --0
		nMRD <= transport '0';
		Addr <= transport std_logic_vector'("1111111100000000"); --FF00
		Dbus <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		nMRD <= transport '1';
		nMWR <= transport '0';
		Addr <= transport std_logic_vector'("0000000011111111"); --FF
		ALUout <= transport std_logic_vector'("11001101"); --CD
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		nMWR <= transport '1';
		Addr <= transport std_logic_vector'("0000000000000000"); --0
		ALUout <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 320 ns; -- Time=920 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION visit_memory_cfg OF visit_memory_wave IS
	FOR testbench_arch
	END FOR;
END visit_memory_cfg;