📄 ch_tw.ant
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-- E:\VHDL\WAITPAST\DIG_CLK
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 18 11:01:14 2007
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY ch_tw IS
END ch_tw;
ARCHITECTURE testbench_arch OF ch_tw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\vhdl\waitpast\dig_clk\ch_tw.ano";
COMPONENT ch_bcd_integer
PORT (
h1 : In std_logic_vector (3 DOWNTO 0);
h2 : In std_logic_vector (3 DOWNTO 0);
f1 : In std_logic_vector (3 DOWNTO 0);
f2 : In std_logic_vector (3 DOWNTO 0);
m1 : In std_logic_vector (3 DOWNTO 0);
m2 : In std_logic_vector (3 DOWNTO 0);
d1 : Out INTEGER RANGE 0 TO 9;
d2 : Out INTEGER RANGE 0 TO 9;
d3 : Out INTEGER RANGE 0 TO 9;
d4 : Out INTEGER RANGE 0 TO 9;
d5 : Out INTEGER RANGE 0 TO 9;
d6 : Out INTEGER RANGE 0 TO 9
);
END COMPONENT;
SIGNAL h1 : std_logic_vector (3 DOWNTO 0);
SIGNAL h2 : std_logic_vector (3 DOWNTO 0);
SIGNAL f1 : std_logic_vector (3 DOWNTO 0);
SIGNAL f2 : std_logic_vector (3 DOWNTO 0);
SIGNAL m1 : std_logic_vector (3 DOWNTO 0);
SIGNAL m2 : std_logic_vector (3 DOWNTO 0);
SIGNAL d1 : INTEGER RANGE 0 TO 9;
SIGNAL d2 : INTEGER RANGE 0 TO 9;
SIGNAL d3 : INTEGER RANGE 0 TO 9;
SIGNAL d4 : INTEGER RANGE 0 TO 9;
SIGNAL d5 : INTEGER RANGE 0 TO 9;
SIGNAL d6 : INTEGER RANGE 0 TO 9;
BEGIN
UUT : ch_bcd_integer
PORT MAP (
h1 => h1,
h2 => h2,
f1 => f1,
f2 => f2,
m1 => m1,
m2 => m2,
d1 => d1,
d2 => d2,
d3 => d3,
d4 => d4,
d5 => d5,
d6 => d6
);
PROCESS -- Annotate outputs process
VARIABLE TX_TIME : INTEGER :=0;
PROCEDURE ANNOTATE_d1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",d1,"));
STD.TEXTIO.write(TX_LOC, d1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_d2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",d2,"));
STD.TEXTIO.write(TX_LOC, d2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_d3(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",d3,"));
STD.TEXTIO.write(TX_LOC, d3);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_d4(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",d4,"));
STD.TEXTIO.write(TX_LOC, d4);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_d5(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",d5,"));
STD.TEXTIO.write(TX_LOC, d5);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_d6(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",d6,"));
STD.TEXTIO.write(TX_LOC, d6);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
BEGIN
CHECK_LOOP : LOOP
WAIT FOR 50 ns;
TX_TIME := TX_TIME + 50;
ANNOTATE_d1(TX_TIME);
ANNOTATE_d2(TX_TIME);
ANNOTATE_d3(TX_TIME);
ANNOTATE_d4(TX_TIME);
ANNOTATE_d5(TX_TIME);
ANNOTATE_d6(TX_TIME);
WAIT FOR 50 ns;
TX_TIME := TX_TIME + 50;
END LOOP CHECK_LOOP;
END PROCESS;
PROCESS
VARIABLE TX_OUT : LINE;
BEGIN
-- --------------------
h1 <= transport std_logic_vector'("0000"); --0
h2 <= transport std_logic_vector'("0010"); --2
f1 <= transport std_logic_vector'("0000"); --0
f2 <= transport std_logic_vector'("0100"); --4
m1 <= transport std_logic_vector'("0101"); --5
m2 <= transport std_logic_vector'("0000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=100 ns
h1 <= transport std_logic_vector'("0001"); --1
h2 <= transport std_logic_vector'("0010"); --2
f1 <= transport std_logic_vector'("0011"); --3
f2 <= transport std_logic_vector'("0100"); --4
m1 <= transport std_logic_vector'("0101"); --5
m2 <= transport std_logic_vector'("0110"); --6
-- --------------------
WAIT FOR 100 ns; -- Time=200 ns
h1 <= transport std_logic_vector'("0001"); --1
h2 <= transport std_logic_vector'("0010"); --2
f1 <= transport std_logic_vector'("0011"); --3
f2 <= transport std_logic_vector'("0100"); --4
m1 <= transport std_logic_vector'("0101"); --5
m2 <= transport std_logic_vector'("0110"); --6
-- --------------------
WAIT FOR 100 ns; -- Time=300 ns
h1 <= transport std_logic_vector'("0001"); --1
h2 <= transport std_logic_vector'("0010"); --2
f1 <= transport std_logic_vector'("0011"); --3
f2 <= transport std_logic_vector'("0100"); --4
m1 <= transport std_logic_vector'("0101"); --5
m2 <= transport std_logic_vector'("0110"); --6
-- --------------------
WAIT FOR 100 ns; -- Time=400 ns
h1 <= transport std_logic_vector'("0001"); --1
h2 <= transport std_logic_vector'("0010"); --2
f1 <= transport std_logic_vector'("0011"); --3
f2 <= transport std_logic_vector'("0100"); --4
m1 <= transport std_logic_vector'("0101"); --5
m2 <= transport std_logic_vector'("0110"); --6
-- --------------------
WAIT FOR 100 ns; -- Time=500 ns
h1 <= transport std_logic_vector'("0001"); --1
h2 <= transport std_logic_vector'("0010"); --2
f1 <= transport std_logic_vector'("0011"); --3
f2 <= transport std_logic_vector'("0100"); --4
m1 <= transport std_logic_vector'("0101"); --5
m2 <= transport std_logic_vector'("0110"); --6
-- --------------------
WAIT FOR 100 ns; -- Time=600 ns
h1 <= transport std_logic_vector'("0001"); --1
h2 <= transport std_logic_vector'("0010"); --2
f1 <= transport std_logic_vector'("0011"); --3
f2 <= transport std_logic_vector'("0100"); --4
m2 <= transport std_logic_vector'("0110"); --6
-- --------------------
WAIT FOR 150 ns; -- Time=750 ns
-- --------------------
STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed"
SEVERITY FAILURE;
END PROCESS;
END testbench_arch;
CONFIGURATION ch_bcd_integer_cfg OF ch_tw IS
FOR testbench_arch
END FOR;
END ch_bcd_integer_cfg;
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