lock_tw.ant

来自「四人抢答器的实现」· ANT 代码 · 共 203 行

-- E:\VHDL\WAITPAST\QIANGDAQI4REN
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sat Mar 24 14:41:25 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY lock_tw IS
END lock_tw;

ARCHITECTURE testbench_arch OF lock_tw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\vhdl\waitpast\qiangdaqi4ren\lock_tw.ano";
	COMPONENT lock
		PORT (
			d1 : In  std_logic;
			d2 : In  std_logic;
			d3 : In  std_logic;
			d4 : In  std_logic;
			clk : In  std_logic;
			clr : In  std_logic;
			q1 : Out  std_logic;
			q2 : Out  std_logic;
			q3 : Out  std_logic;
			q4 : Out  std_logic;
			alm : Out  std_logic
		);
	END COMPONENT;

	SIGNAL d1 : std_logic;
	SIGNAL d2 : std_logic;
	SIGNAL d3 : std_logic;
	SIGNAL d4 : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL clr : std_logic;
	SIGNAL q1 : std_logic;
	SIGNAL q2 : std_logic;
	SIGNAL q3 : std_logic;
	SIGNAL q4 : std_logic;
	SIGNAL alm : std_logic;

BEGIN
	UUT : lock
	PORT MAP (
		d1 => d1,
		d2 => d2,
		d3 => d3,
		d4 => d4,
		clk => clk,
		clr => clr,
		q1 => q1,
		q2 => q2,
		q3 => q3,
		q4 => q4,
		alm => alm
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_q1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",q1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_q2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",q2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_q3(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",q3,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q3);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_q4(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",q4,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q4);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_alm(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",alm,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, alm);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ms;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ms;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_q1(TX_TIME);
		ANNOTATE_q2(TX_TIME);
		ANNOTATE_q3(TX_TIME);
		ANNOTATE_q4(TX_TIME);
		ANNOTATE_alm(TX_TIME);
		WAIT FOR 40 ms;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ms;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		d1 <= transport '0';
		d2 <= transport '0';
		d3 <= transport '0';
		d4 <= transport '0';
		clr <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=100 ms
		clr <= transport '0';
		-- --------------------
		WAIT FOR 200 ms; -- Time=300 ms
		d1 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=400 ms
		d1 <= transport '0';
		-- --------------------
		WAIT FOR 320 ms; -- Time=720 ms
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION lock_cfg OF lock_tw IS
	FOR testbench_arch
	END FOR;
END lock_cfg;