code_wave.ant

16位cpu设计VHDL源码

-- C:\XILINX\BIN\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:40:12 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY code_wave IS
END code_wave;

ARCHITECTURE testbench_arch OF code_wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\xilinx\bin\mycpu16\code_wave.ano";
	COMPONENT code
		PORT (
			RST : In  std_logic;
			T0 : In  std_logic;
			T1 : In  std_logic;
			clk : In  std_logic;
			PCupdate : In  std_logic;
			PCnew : In  std_logic_vector (15 DOWNTO 0);
			IRnew : In  std_logic_vector (15 DOWNTO 0);
			PCload : Out  std_logic;
			IRout : Out  std_logic_vector (15 DOWNTO 0);
			PCout : Out  std_logic_vector (15 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL RST : std_logic;
	SIGNAL T0 : std_logic;
	SIGNAL T1 : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL PCupdate : std_logic;
	SIGNAL PCnew : std_logic_vector (15 DOWNTO 0);
	SIGNAL IRnew : std_logic_vector (15 DOWNTO 0);
	SIGNAL PCload : std_logic;
	SIGNAL IRout : std_logic_vector (15 DOWNTO 0);
	SIGNAL PCout : std_logic_vector (15 DOWNTO 0);

BEGIN
	UUT : code
	PORT MAP (
		RST => RST,
		T0 => T0,
		T1 => T1,
		clk => clk,
		PCupdate => PCupdate,
		PCnew => PCnew,
		IRnew => IRnew,
		PCload => PCload,
		IRout => IRout,
		PCout => PCout
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_PCload(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",PCload,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PCload);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_IRout(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",IRout,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, IRout);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_PCout(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",PCout,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PCout);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_PCload(TX_TIME);
		ANNOTATE_IRout(TX_TIME);
		ANNOTATE_PCout(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		RST <= transport '0';
		T0 <= transport '0';
		T1 <= transport '0';
		PCupdate <= transport '0';
		PCnew <= transport std_logic_vector'("0000000000000000"); --0
		IRnew <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		RST <= transport '1';
		T0 <= transport '1';
		IRnew <= transport std_logic_vector'("0101000010101011"); --50AB
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		T0 <= transport '0';
		T1 <= transport '1';
		IRnew <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		T0 <= transport '1';
		T1 <= transport '0';
		IRnew <= transport std_logic_vector'("0101011111111111"); --57FF
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		T0 <= transport '0';
		T1 <= transport '1';
		IRnew <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		T0 <= transport '1';
		T1 <= transport '0';
		IRnew <= transport std_logic_vector'("0001011100000000"); --1700
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		T0 <= transport '0';
		T1 <= transport '1';
		IRnew <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		T0 <= transport '1';
		T1 <= transport '0';
		PCupdate <= transport '1';
		PCnew <= transport std_logic_vector'("1111111100000001"); --FF01
		IRnew <= transport std_logic_vector'("0110000000000000"); --6000
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		T0 <= transport '0';
		T1 <= transport '1';
		PCupdate <= transport '0';
		PCnew <= transport std_logic_vector'("0000000000000000"); --0
		IRnew <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		T0 <= transport '1';
		T1 <= transport '0';
		IRnew <= transport std_logic_vector'("0100000100000000"); --4100
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		T0 <= transport '0';
		T1 <= transport '1';
		IRnew <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		T0 <= transport '1';
		T1 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		T0 <= transport '0';
		T1 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		T0 <= transport '1';
		T1 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		T0 <= transport '0';
		T1 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		T1 <= transport '0';
		-- --------------------
		WAIT FOR 420 ns; -- Time=1920 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION code_cfg OF code_wave IS
	FOR testbench_arch
	END FOR;
END code_cfg;