wave.ant

verilog 编写的pic16c5x时钟模块

// E:\FPGA\CLKGEN
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Fri May 18 22:21:23 2007

`timescale 1ns/1ns

module wave;
	reg clk;
	reg reset;
	wire clk1;
	wire clk2;
	wire clk3;
	wire clk4;

	defparam UUT.idle = 0;
	defparam UUT.q1 = 1;
	defparam UUT.q2 = 2;
	defparam UUT.q3 = 3;
	defparam UUT.q4 = 4;

	clkgen UUT (
		.clk(clk),
		.reset(reset),
		.clk1(clk1),
		.clk2(clk2),
		.clk3(clk3),
		.clk4(clk4)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clk = 1'b0;
	#10
	clk = 1'b1;
	#10
	ANNOTATE_clk1;
	ANNOTATE_clk2;
	ANNOTATE_clk3;
	ANNOTATE_clk4;
	#40
	clk = 1'b0;
	#40
	clk = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("e:\\fpga\\clkgen\\wave.ano");

	// --------------------
	reset = 1'b0;
	// --------------------
	#100 // Time=100 ns
	reset = 1'b0;
	// --------------------
	#700 // Time=800 ns
	reset = 1'b0;
	// --------------------
	#400 // Time=1200 ns
	reset = 1'b1;
	// --------------------
	#4500 // Time=5700 ns
	reset = 1'b1;
	// --------------------
	#100 // Time=5800 ns
	reset = 1'b1;
	// --------------------
	#100 // Time=5900 ns
	reset = 1'b1;
	// --------------------
	#510 // Time=6410 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_clk1;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,clk1,%b]",
			$time, clk1);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_clk2;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,clk2,%b]",
			$time, clk2);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_clk3;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,clk3,%b]",
			$time, clk3);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_clk4;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,clk4,%b]",
			$time, clk4);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule