lcd_tw.ant

数字钟的实现

-- E:\VHDL\PAST\DIG_CLK
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 17 20:33:46 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY lcd_tw IS
END lcd_tw;

ARCHITECTURE testbench_arch OF lcd_tw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\vhdl\past\dig_clk\lcd_tw.ano";
	COMPONENT lcd
		PORT (
			clk : In  std_logic;
			Reset : In  std_logic;
			lcd_rs : Out  std_logic;
			lcd_rw : Out  std_logic;
			lcd_e : Buffer  std_logic;
			din1 : In  INTEGER RANGE 0 TO 9;
			din2 : In  INTEGER RANGE 0 TO 9;
			din3 : In  INTEGER RANGE 0 TO 9;
			din4 : In  INTEGER RANGE 0 TO 9;
			din5 : In  INTEGER RANGE 0 TO 9;
			din6 : In  INTEGER RANGE 0 TO 9;
			data : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clk : std_logic;
	SIGNAL Reset : std_logic;
	SIGNAL lcd_rs : std_logic;
	SIGNAL lcd_rw : std_logic;
	SIGNAL lcd_e : std_logic;
	SIGNAL din1 : INTEGER RANGE 0 TO 9;
	SIGNAL din2 : INTEGER RANGE 0 TO 9;
	SIGNAL din3 : INTEGER RANGE 0 TO 9;
	SIGNAL din4 : INTEGER RANGE 0 TO 9;
	SIGNAL din5 : INTEGER RANGE 0 TO 9;
	SIGNAL din6 : INTEGER RANGE 0 TO 9;
	SIGNAL data : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : lcd
	PORT MAP (
		clk => clk,
		Reset => Reset,
		lcd_rs => lcd_rs,
		lcd_rw => lcd_rw,
		lcd_e => lcd_e,
		din1 => din1,
		din2 => din2,
		din3 => din3,
		din4 => din4,
		din5 => din5,
		din6 => din6,
		data => data
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_lcd_rs(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",lcd_rs,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, lcd_rs);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_lcd_rw(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",lcd_rw,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, lcd_rw);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_data(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",data,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_lcd_e(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",lcd_e,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, lcd_e);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_lcd_rs(TX_TIME);
		ANNOTATE_lcd_rw(TX_TIME);
		ANNOTATE_data(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		Reset <= transport '0';
		din1 <= transport 1; -- 1
		din2 <= transport 1; -- 1
		din3 <= transport 5; -- 5
		din4 <= transport 9; -- 9
		din5 <= transport 5; -- 5
		din6 <= transport 5; -- 5
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		din1 <= transport 1; -- 1
		din2 <= transport 1; -- 1
		din3 <= transport 5; -- 5
		din4 <= transport 9; -- 9
		din5 <= transport 5; -- 5
		din6 <= transport 6; -- 6
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		din1 <= transport 1; -- 1
		din2 <= transport 1; -- 1
		din3 <= transport 5; -- 5
		din4 <= transport 9; -- 9
		din5 <= transport 5; -- 5
		din6 <= transport 7; -- 7
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		din1 <= transport 1; -- 1
		din2 <= transport 1; -- 1
		din3 <= transport 5; -- 5
		din4 <= transport 9; -- 9
		din5 <= transport 5; -- 5
		din6 <= transport 8; -- 8
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		din1 <= transport 1; -- 1
		din2 <= transport 1; -- 1
		din3 <= transport 5; -- 5
		din4 <= transport 9; -- 9
		din5 <= transport 5; -- 5
		din6 <= transport 9; -- 9
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		din1 <= transport 1; -- 1
		din2 <= transport 2; -- 2
		din3 <= transport 0; -- 0
		din4 <= transport 0; -- 0
		din5 <= transport 0; -- 0
		din6 <= transport 0; -- 0
		-- --------------------
		WAIT FOR 210 ns; -- Time=710 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION lcd_cfg OF lcd_tw IS
	FOR testbench_arch
	END FOR;
END lcd_cfg;