count100.v

来自「60秒秒表设计」· Verilog 代码 · 共 44 行

//8bit 100-band counter
module count100(clk,rst,en,load,q,carry);
input  clk,rst,en,load;
output [7:0]q;
output carry;

reg[3:0] high1;
reg[3:0] low1;

always@(posedge clk or negedge rst)
begin
  if(rst==1'b0)
    begin
      high1[3:0]=0; 
	  low1[3:0]=0; 
    end
  else if(load==1'b0)
    begin
      high1[3:0]=0; 
	  low1[3:0]=0; 
    end
  else if(en==1'b0)
    begin
      high1[3:0]=high1[3:0]; 
	  low1[3:0]=low1[3:0];
    end
  else if(low1[3:0]==4'd9)
    begin
      low1[3:0]=4'd0;
      if(high1[3:0]==4'd9)
        begin
          high1[3:0]=4'd0;
        end
      else
        high1[3:0]=high1[3:0]+1'b1;
    end
  else
      low1[3:0]=low1[3:0]+1'b1;
end

assign carry=(low1[3:0]==4'd9&&high1[3:0]==4'd9)?1'b1:1'b0;
assign q={high1,low1};

endmodule