top_watch.map.qmsg

60秒秒表设计

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "switch switch:shot1 " "Info: Elaborating entity \"switch\" for hierarchy \"switch:shot1\"" {  } { { "top_watch.v" "shot1" { Text "D:/60s项目/60s/top_watch.v" 26 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "state state:state1 " "Info: Elaborating entity \"state\" for hierarchy \"state:state1\"" {  } { { "top_watch.v" "state1" { Text "D:/60s项目/60s/top_watch.v" 28 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:counts " "Info: Elaborating entity \"counter\" for hierarchy \"counter:counts\"" {  } { { "top_watch.v" "counts" { Text "D:/60s项目/60s/top_watch.v" 29 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "qout counter.v(24) " "Warning (10235): Verilog HDL Always Construct warning at counter.v(24): variable \"qout\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "counter.v" "" { Text "D:/60s项目/60s/counter.v" 24 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count100 counter:counts\|count100:count_1 " "Info: Elaborating entity \"count100\" for hierarchy \"counter:counts\|count100:count_1\"" {  } { { "counter.v" "count_1" { Text "D:/60s项目/60s/counter.v" 11 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count60 counter:counts\|count60:count_2 " "Info: Elaborating entity \"count60\" for hierarchy \"counter:counts\|count60:count_2\"" {  } { { "counter.v" "count_2" { Text "D:/60s项目/60s/counter.v" 12 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dtlatch dtlatch:dtlatch1 " "Info: Elaborating entity \"dtlatch\" for hierarchy \"dtlatch:dtlatch1\"" {  } { { "top_watch.v" "dtlatch1" { Text "D:/60s项目/60s/top_watch.v" 30 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "select select:select1 " "Info: Elaborating entity \"select\" for hierarchy \"select:select1\"" {  } { { "top_watch.v" "select1" { Text "D:/60s项目/60s/top_watch.v" 31 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "select.v(9) " "Info (10264): Verilog HDL Case Statement information at select.v(9): all case item expressions in this case statement are onehot" {  } { { "select.v" "" { Text "D:/60s项目/60s/select.v" 9 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7_dec seg7_dec:seg7 " "Info: Elaborating entity \"seg7_dec\" for hierarchy \"seg7_dec:seg7\"" {  } { { "top_watch.v" "seg7" { Text "D:/60s项目/60s/top_watch.v" 32 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter:counts\|count60:count_2\|high2\[0\]~20 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter:counts\|count60:count_2\|high2\[0\]~20\"" {  } { { "count60.v" "high2\[0\]~20" { Text "D:/60s项目/60s/count60.v" 20 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 247 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "counter:counts\|count60:count_2\|lpm_counter:high2_rtl_0 " "Info: Elaborated megafunction instantiation \"counter:counts\|count60:count_2\|lpm_counter:high2_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "div192:div1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"div192:div1\|lpm_add_sub:Add0\"" {  } { { "div192.v" "" { Text "D:/60s项目/60s/div192.v" 22 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/70/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "div192:div1\|lpm_add_sub:Add0\|addcore:adder\[0\] div192:div1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"div192:div1\|lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"div192:div1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 278 9 0 } } { "div192.v" "" { Text "D:/60s项目/60s/div192.v" 22 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "div192:div1\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"div192:div1\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "div192.v" "" { Text "D:/60s项目/60s/div192.v" 22 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "div192:div1\|lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node div192:div1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"div192:div1\|lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"div192:div1\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "div192.v" "" { Text "D:/60s项目/60s/div192.v" 22 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "div192:div1\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"div192:div1\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "div192.v" "" { Text "D:/60s项目/60s/div192.v" 22 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}