div192.v

来自「60秒秒表设计」· Verilog 代码 · 共 26 行

module div192(clk768,rst,clk4);
input clk768,rst;
output clk4;
reg clk4;
reg[7:0] count96;

always@(posedge clk768 or negedge rst)
  begin
    if(rst==0)
      begin  
         clk4<=0;
         count96<=0;
      end
    else if(count96==8'd95)
      begin
          clk4<=~clk4;
          count96<=8'd0;
      end
    else
      begin
          clk4<=clk4;
          count96<=count96+1'd1;
      end
  end

endmodule