📄 top_watch.fit.rpt
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; div192:div1|count96[5] ; 4 ;
; state:state1|sel.state_bit_0 ; 4 ;
+----------------------------------------------------------------+---------+
+-------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+--------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+--------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 138 / 288 ( 48 % ) ;
; PIAs ; 151 / 288 ( 52 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 18.88) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 1 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 1 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 2 ;
; 21 - 23 ; 3 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 1 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 11.88) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 4 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 7 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.38) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
+-------------------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC13 ; rst, state:state1|sel.state_bit_2, switch:shot2|swout, state:state1|sel.state_bit_1, state:state1|sel.state_bit_0, switch:shot1|swout, clk ; state:state1|hold, state:state1|sel.state_bit_0, state:state1|sel.state_bit_1, state:state1|crst ;
; A ; LC2 ; rst, clk ; div_4:div2|drv_cnt:drv1|q[1], div_4:div2|drv_dec:drv2|Decoder0~35, div_4:div2|drv_dec:drv2|Decoder0~37, div_4:div2|drv_dec:drv2|Decoder0~39, select:select1|Mux3~260, div_4:div2|drv_dec:drv2|Decoder0~41, counter:counts|count100:count_1|low1[0], counter:counts|count100:count_1|low1[1], counter:counts|count100:count_1|low1[2], counter:counts|count100:count_1|low1[3], counter:counts|count100:count_1|high1[0], counter:counts|count100:count_1|high1[1], counter:counts|count100:count_1|high1[2], counter:counts|count100:count_1|high1[3], select:select1|Mux2~252, select:select1|Mux1~255, select:select1|Mux0~255, select:select1|Mux3~265, seg7_dec:seg7|Decoder0~48, seg7_dec:seg7|WideOr0~104, seg7_dec:seg7|select~154, seg7_dec:seg7|Mux3~263, seg7_dec:seg7|Mux0~342, seg7_dec:seg7|Mux0~347, seg7_dec:seg7|Mux2~540, seg7_dec:seg7|Mux2~546, seg7_dec:seg7|Mux2~549, seg7_dec:seg7|Mux1~468, seg7_dec:seg7|Mux1~469, seg7_dec:seg7|Mux1~470, seg7_dec:seg7|Mux1~475, seg7_dec:seg7|WideOr0~106, seg7_dec:seg7|select~156, seg7_dec:seg7|Mux3~265, seg7_dec:seg7|Mux0~349, seg7_dec:seg7|Mux0~355, seg7_dec:seg7|Mux1~478 ;
; A ; LC15 ; rst, swst, clk ; state:state1|sel.state_bit_0, state:state1|sel.state_bit_2, state:state1|sel.state_bit_1 ;
; A ; LC14 ; rst, swsp, clk ; state:state1|sel.state_bit_0, state:state1|sel.state_bit_2, state:state1|sel.state_bit_1 ;
; A ; LC1 ; rst, div_4:div2|drv_cnt:drv1|q[0], clk ; div_4:div2|drv_dec:drv2|Decoder0~35, div_4:div2|drv_dec:drv2|Decoder0~37, div_4:div2|drv_dec:drv2|Decoder0~39, select:select1|Mux3~260, div_4:div2|drv_dec:drv2|Decoder0~41, counter:counts|count100:count_1|low1[0], counter:counts|count100:count_1|low1[1], counter:counts|count100:count_1|low1[2], counter:counts|count100:count_1|low1[3], counter:counts|count100:count_1|high1[0], counter:counts|count100:count_1|high1[1], counter:counts|count100:count_1|high1[2], counter:counts|count100:count_1|high1[3], select:select1|Mux2~252, select:select1|Mux1~255, select:select1|Mux0~255, select:select1|Mux3~265, seg7_dec:seg7|Decoder0~48, seg7_dec:seg7|WideOr0~104, seg7_dec:seg7|select~154, seg7_dec:seg7|Mux3~263, seg7_dec:seg7|Mux0~342, seg7_dec:seg7|Mux0~347, seg7_dec:seg7|Mux2~540, seg7_dec:seg7|Mux2~546, seg7_dec:seg7|Mux2~549, seg7_dec:seg7|Mux1~468, seg7_dec:seg7|Mux1~469, seg7_dec:seg7|Mux1~470, seg7_dec:seg7|Mux1~475, seg7_dec:seg7|WideOr0~106, seg7_dec:seg7|select~156, seg7_dec:seg7|Mux3~265, seg7_dec:seg7|Mux0~349, seg7_dec:seg7|Mux0~355, seg7_dec:seg7|Mux1~478 ;
; A ; LC7 ; state:state1|sel.state_bit_1, rst, state:state1|sel.state_bit_0, state:state1|sel.state_bit_2, state:state1|hold, clk ; state:state1|hold, dtlatch:dtlatch1|sel_din[0], dtlatch:dtlatch1|sel_din[1], dtlatch:dtlatch1|sel_din[2], dtlatch:dtlatch1|sel_din[3], dtlatch:dtlatch1|sel_din[5], dtlatch:dtlatch1|sel_din[6], dtlatch:dtlatch1|sel_din[7], dtlatch:dtlatch1|sel_din[8], dtlatch:dtlatch1|sel_din[9], dtlatch:dtlatch1|sel_din[10], dtlatch:dtlatch1|sel_din[11], dtlatch:dtlatch1|sel_din[12], dtlatch:dtlatch1|sel_din[13], dtlatch:dtlatch1|sel_din[14], dtlatch:dtlatch1|sel_din[15], dtlatch:dtlatch1|sel_din[4] ;
; A ; LC10 ; rst, switch:shot2|swout, switch:shot1|swout, state:state1|sel.state_bit_1, state:state1|sel.state_bit_2, clk ; state:state1|hold, state:state1|sel.state_bit_0, state:state1|sel.state_bit_2, state:state1|con, state:state1|sel.state_bit_1, state:state1|crst ;
; A ; LC12 ; state:state1|sel.state_bit_2, rst, state:state1|con, clk ; state:state1|con, counter:counts|count100:count_1|low1[0], counter:counts|count100:count_1|low1[1], counter:counts|count100:count_1|low1[2], counter:counts|count100:count_1|low1[3], counter:counts|count100:count_1|high1[0], counter:counts|count100:count_1|high1[1], counter:counts|count100:count_1|high1[2], counter:counts|count100:count_1|high1[3] ;
; A ; LC8 ; rst, state:state1|sel.state_bit_0, state:state1|sel.state_bit_2, switch:shot2|swout, switch:shot1|swout, state:state1|sel.state_bit_1, clk ; state:state1|hold, state:state1|sel.state_bit_0, state:state1|sel.state_bit_2, state:state1|sel.state_bit_1, state:state1|crst ⌨️ 快捷键说明
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