state.v

来自「60秒秒表设计」· Verilog 代码 · 共 66 行

module state(clk4,rst,st,sp,con,crst,hold);
input clk4,rst,st,sp;
output con,crst,hold;
reg con,crst,hold;

reg[2:0] sel;
parameter reset=3'd0,count=3'd1,lap=3'd2,stop1=3'd3,stop2=3'd4;

always@(posedge clk4 or negedge rst)
  begin
    if(rst==1'b0)
      begin
        sel<=reset;
      end
    else
      begin
        case(sel)
          reset: begin
                   con<=1'b0; crst<=1'b1; hold<=1'b0; 
                   if(st==1'b1&&sp==1'b0)
                     sel<=count;
                   else if(st==1'b0&&sp==1'b1)
                     sel<=reset;
                 end
          count: begin
                     con<=1'b1; crst<=1'b0; hold<=1'b0;
                   if(st==1'b1&&sp==1'b0)
                     sel<=stop1;
                   else if(st==1'b0&&sp==1'b1)
                     sel<=lap;
                   else
                      sel<=count;
                 end
            lap: begin
                     con<=1'b1; crst<=1'b0; hold<=1'b1;
                   if(st==1'b1&&sp==1'b0)
                     sel<=stop2;
                   else if(st==1'b0&&sp==1'b1)
                     sel<=count;
                   else
                     sel<=lap;
                 end
          stop1: begin
                     con<=1'b0; crst<=1'b0; hold<=1'b0;
                   if(st==1'b1&&sp==1'b0)
                     sel<=count;
                   else if(st==1'b0&&sp==1'b1)
                     sel<=reset;
                   else
                     sel<=stop1;
                 end
          stop2: begin
                     con<=1'b0; crst<=1'b0; hold<=1'b1;
                   if(st==1'b1&&sp==1'b0)
                     sel<=lap;
                   else if(st==1'b0&&sp==1'b1)
                     sel<=stop1;
                   else
                     sel<=stop2;
                 end
           default: sel<=reset;
        endcase
      end
  end
endmodule