drv_dec.v

60秒秒表设计

module drv_dec(din,dout);
input [1:0]din;
output [3:0]dout;

reg [3:0]dout;

always @(din)
begin
  case(din)
    2'h0:dout=1;
    2'h1:dout=2;
    2'h2:dout=4;
    2'h3:dout=8;
   default: dout=4'bxxxx;
   endcase
end
endmodule