top_watch.v

来自「60秒秒表设计」· Verilog 代码 · 共 34 行

//60s watch of top module
module top_watch(clk768,rst,clk,swst,swsp,clk400,drive,segment,count,dec_din);
input clk768,clk;
input rst;
input swst,swsp;
output clk400;
output[3:0] drive,dec_din;
output[7:0] segment;
output[15:0] count;

wire stpls,sppls;
wire con,crst,hold;
wire en;
//wire[1:0] carry;
wire[15:0] qout;
wire[15:0] sel_din;
wire[3:0] dout;

assign en=con&drive[0];
assign segment[7]=drive[2];
assign count=qout;
assign dec_din=dout;

div192  div1(clk768,rst,clk400);
div_4   div2(clk,rst,drive);
switch  shot1(clk,rst,swst,stpls);
switch  shot2(clk,rst,swsp,sppls);
state   state1(clk,rst,stpls,sppls,con,crst,hold);
counter counts(clk,rst,en,crst,qout);
dtlatch dtlatch1(clk,hold,rst,qout,sel_din);
select  select1(drive,sel_din[3:0],sel_din[7:4],sel_din[11:8],sel_din[15:12],dout);
seg7_dec seg7(dout,segment[6:0]);

endmodule