count60.v

来自「60秒秒表设计」· Verilog 代码 · 共 53 行

//8bit 100-band counter
module count60(clk,rst,en,load,q,carry);
input  clk,rst,en,load;
output[7:0] q;

output carry;
reg carry;

reg[3:0] high2;
reg[3:0] low2;

always@(posedge clk or negedge rst)
begin
  if(rst==1'b0)
    begin
      high2[3:0]=0; 
	  low2[3:0]=0; 
      carry=1'b0;
    end
  else if(load==1'b0)
    begin
      high2[3:0]=0; 
	  low2[3:0]=0; 
      carry=1'b0;
    end
  else if(en==1'b0)
    begin
      high2[3:0]=high2[3:0]; 
	  low2[3:0]=low2[3:0];
      carry=carry;
    end
  else if(low2[3:0]==4'd9)
    begin
      low2[3:0]=4'd0;
      if(high2[3:0]==4'd5)
        begin
          carry=1'b1;
          high2[3:0]=4'd6;
          low2[3:0]=4'd0;
        end
      else
        high2[3:0]=high2[3:0]+1'b1;
    end
  else
    begin
      low2[3:0]=low2[3:0]+1'b1;
      carry=1'b0;
    end
end

assign q={high2,low2};

endmodule