div_4.v

60秒秒表设计

module div_4(clk4,rst,drive);
input clk4,rst;
output[3:0] drive;

wire[1:0] drv_count;

drv_cnt drv1(.clk(clk4),.rst(rst),.q(drv_count));
drv_dec drv2(.din(drv_count),.dout(drive));

endmodule