tendiv4.v

4位数字频率计的verilog HDL设计

module TenDiv4(BCDout,Clr,Clock);
	   
input Clock;
input Clr;
output [3:0]BCDout;

reg [3:0] BCDout;


always @( __________ Clock or ____________ Clr)
   if(Clr)
    	  BCDout <= 0;
   else if( ___________ )
           _______________;
        else
           ______________;


endmodule