divstream.v

来自「4位数字频率计的verilog HDL设计」· Verilog 代码 · 共 27 行

module DivStream(Sel,Latch,Catch,Clear,Clock);

input Clock; //8MHz

output Latch;
output Catch;
output Clear;
output [2:0]Sel;

reg [2:0] Sel;

wire F800KHz,F80KHz,F8KHz;
wire F800Hz,F80HzW;

TenDiv  DFto800KHz(F800KHz,Clock);
TenDiv  DFto80KHz(F80KHz,F800KHz);
TenDiv  DFto8KHz(F8KHz,F80KHz);
TenDiv  DFto800Hz(F800Hz,F8KHz);
TenDiv  DFto80Hz(F80HzW,F800Hz);

always @(posedge F8KHz)
   Sel <= Sel +1;

Gen_Seq Genseq1(Latch,Catch,Clear,F80HzW);

endmodule