count.v

来自「用verillog HDL 写的数字频率计.在实验箱上测试通过」· Verilog 代码 · 共 28 行

module count(clkout,bcxh,dis);
	input clkout,bcxh;
	output [WIDTH - 1:0] dis;
	reg [WIDTH - 1:0] dis;
	reg [WIDTH - 1:0] counter2;
	reg i;


	parameter WIDTH = 32;

	always@(posedge bcxh)
		begin
			if(clkout)//enable count
				begin
					counter2 <= counter2 + 1;
					i <= 1'b0;//couunting flag 0
				end
			else//disable count
				if(i == 0)
					begin 
						i   <= 1'b1; //display
						dis <= counter2;
						counter2<=0;
					end
		end
endmodule