fenpin.v

来自「用verillog HDL 写的数字频率计.在实验箱上测试通过」· Verilog 代码 · 共 20 行

module fenpin(clk,clkout);
input clk;
output clkout;
reg clkout;
reg [WIDTH - 1:0] counter1;

parameter WIDTH = 32;
parameter N = 1000;
always@(posedge clk)
begin 
		if(counter1 == N / 2 - 1)
			begin
				 clkout <= ~clkout;
				 counter1 <= 0;
			end
		else
			counter1 <= counter1 + 1;
end
endmodule