suocun.v

来自「用verillog HDL 写的数字频率计.在实验箱上测试通过」· Verilog 代码 · 共 66 行

module suocun (clk,reset,dis,leds,ledb,ledq,ld);
input clk,reset;
input [16:0] dis;
output [3:0] leds,ledb,ledq;
output [2:0] ld;
reg [3:0] leds,ledb,ledq;
reg [2:0] ld;
reg [16:0] disz;
reg [3:0] state;

parameter s1=0001,s2=0010,s3=0100,s4=1000;

always@(posedge clk)
 begin
  if(reset==0)
   begin
    case(state)
      s1:
        begin
          disz<=dis;
          state<=s2;
        end
      s2:
        begin
          case(ld)
              3'b100:disz<=dis/10;
              3'b010:disz<=dis/100;
              3'b001:disz<=dis/1000;
           default:
            begin
              disz<=disz/10;
              ld<=3'b100;
            end
           endcase
            state<=s3;
         end
       s3:
         begin
           if((disz>999)&&(ld>3'b001))
             ld<=ld<<1;
           else if((disz>99)&&(ld<3'b100))
            begin
             ld<=ld>>1;
            end
            state<=s4;
         end
       s4:
         begin
          leds<=disz%10;
          ledb<=(disz/10)%10;
          ledq<=(disz/100)%10;
          state<=s1;
         end
        default:
         begin
          leds<=0;
          ledb<=0;
          ledq<=0;
          ld<=3'b100;
          state<=s1;
         end
    endcase
    end
  end
endmodule