dec.v

来自「用verillog HDL 写的数字频率计.在实验箱上测试通过」· Verilog 代码 · 共 29 行

module dec(cin,op,seg);
input op;
input [3:0] cin;
output [7:0] seg;
reg [7:0] seg;

always@(cin or op)
begin
  if(op)
    seg[7] = ~1'b0;
  else 
    seg[7] = ~1'b1;
  case(cin)
    4'b0000: seg[6:0] = 7'b0111111;
    4'b0001: seg[6:0] = 7'b0000110;
    4'b0010: seg[6:0] = 7'b1011011;
    4'b0011: seg[6:0] = 7'b1001111;
    4'b0100: seg[6:0] = 7'b1100110;
    4'b0101: seg[6:0] = 7'b1101101;
    4'b0110: seg[6:0] = 7'b1111101;
    4'b0111: seg[6:0] = 7'b0000111;
    4'b1000: seg[6:0] = 7'b1111111;
    4'b1001: seg[6:0] = 7'b1101111;
    default:
             seg[6:0] = 7'b0111111;
  endcase
 end
endmodule