scan.v

来自「用verillog HDL 写的数字频率计.在实验箱上测试通过」· Verilog 代码 · 共 63 行

module scan(clk,ledg,leds,ledb,op,BCDo,BIT,dp);
	input clk;
	input [3:0] ledg,leds,ledb;
	input [2:0] op;
	
	output [3:0] BCDo;
	output [2:0] BIT;
	output      dp;
	reg dp;
	reg [3:0] BCDo;
	reg [2:0] BIT;
	
	reg [1:0] count;
	always @(posedge clk)
		begin
			count <= count + 1;
		end
		
	always @(count or ledg or leds or ledb)
		begin
			case(count)
			2'b00:
				BCDo = ledg;
			2'b01:
				BCDo = leds;
			2'b10:
				BCDo = ledb;
			2'b11:
				BCDo = 4'hf;
			endcase
		end
		
	always @(count or op or dp)
		begin
			case(count)
			2'b00:begin
					BIT = 3'b001;
					if(op == 3'b001)
						dp = 1'b1;
					else 
						dp = 1'b0; 
				end
			2'b01:begin
					BIT <= 3'b010;
					if(op == 3'b010)
						dp = 1'b1;
					else 
						dp = 1'b0; 
				end
			2'b10:begin
					BIT <= 3'b100;
					if(op == 3'b100)
						dp = 1'b1;
					else 
						dp = 1'b0; 
				end
			2'b11:begin
				BIT <= 3'b000;
				dp = 1'b0;
				end
			endcase
		end
endmodule