secondwatch_v.sdo

用VERILOG实现的秒表 用VERILOG实现的秒表

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "secondwatch")
  (DATE "06/14/2008 12:38:44")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|cout_bit.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (1146:1146:1146) (1188:1188:1188))
        (IOPATH datad combout (114:114:114) (114:114:114))
        (IOPATH cin combout (621:621:621) (621:621:621))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella0.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (519:519:519) (526:526:526))
        (PORT datac (1306:1306:1306) (1352:1352:1352))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datab cout (583:583:583) (583:583:583))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella0.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2400:2400:2400) (2495:2495:2495))
        (PORT datac (1421:1421:1421) (1467:1467:1467))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella1.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (506:506:506) (515:515:515))
        (PORT datac (1303:1303:1303) (1350:1350:1350))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella1.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2400:2400:2400) (2495:2495:2495))
        (PORT datac (1418:1418:1418) (1465:1465:1465))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella2.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (526:526:526) (535:535:535))
        (PORT datac (1303:1303:1303) (1348:1348:1348))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella2.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2400:2400:2400) (2495:2495:2495))
        (PORT datac (1418:1418:1418) (1463:1463:1463))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella3.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (537:537:537) (545:545:545))
        (PORT datac (1302:1302:1302) (1349:1349:1349))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella3.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2400:2400:2400) (2495:2495:2495))
        (PORT datac (1417:1417:1417) (1464:1464:1464))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella4.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (516:516:516) (524:524:524))
        (PORT datac (1304:1304:1304) (1351:1351:1351))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella4.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2400:2400:2400) (2495:2495:2495))
        (PORT datac (1419:1419:1419) (1466:1466:1466))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella5.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (539:539:539) (547:547:547))
        (PORT datac (1305:1305:1305) (1352:1352:1352))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout (838:838:838) (838:838:838))
        (IOPATH cin cout (208:208:208) (208:208:208))
        (IOPATH cin0 cout (271:271:271) (271:271:271))
        (IOPATH cin1 cout (258:258:258) (258:258:258))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella5.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2400:2400:2400) (2495:2495:2495))
        (PORT datac (1420:1420:1420) (1467:1467:1467))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella6.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (498:498:498) (510:510:510))
        (PORT datac (1411:1411:1411) (1447:1447:1447))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella6.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2472:2472:2472) (2567:2567:2567))
        (PORT datac (1526:1526:1526) (1562:1562:1562))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella7.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (515:515:515) (529:529:529))
        (PORT datac (1410:1410:1410) (1447:1447:1447))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella7.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2472:2472:2472) (2567:2567:2567))
        (PORT datac (1525:1525:1525) (1562:1562:1562))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella11.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (499:499:499) (510:510:510))
        (PORT datac (1422:1422:1422) (1460:1460:1460))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella11.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (2472:2472:2472) (2567:2567:2567))
        (PORT datac (1537:1537:1537) (1575:1575:1575))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1433:1433:1433) (1413:1413:1413))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sload (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sload (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE fenpin_inst\|lpm_counter_component\|auto_generated\|counter_cella8.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (521:521:521) (533:533:533))
        (PORT datac (1410:1410:1410) (1446:1446:1446))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))