rlshifter.v.bak

来自「用VERILOG实现的秒表 用VERILOG实现的秒表」· BAK 代码 · 共 12 行

module rlshifter(clk,reset,q)
  input clk,reset;
  output [3:0] q;
  reg[3:0] q;
  always@(posedge clk or posedge reset)
    begin 
      if(reset==1)
        q<=4'h0;
      else
        q<={q[2:0],q[3]};
    end
endmodule