secondwatch.map.summary

来自「用VERILOG实现的秒表 用VERILOG实现的秒表」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sat Jun 14 12:38:27 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : secondwatch
Top-level Entity Name : secondwatch
Family : Cyclone
Total logic elements : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge