top_fd_iii.v

用VERILOG实现的秒表 用VERILOG实现的秒表

module secondwatch(
//	Clock Input
	input clkin,	// 20MHz晶振
//	Reset Button
	input reset_n,  // 低电平复位
//	Push Button
	input [8:0] key,    //9个按键（9~1）。按下为0，松开为1。
//	Toggle Switch
	input [0:3] switch, //按实验箱的位序标识，SW0在最左边。拨向上为0，拨向下为1。
//	LED
	output [0:7] led,	//LED0~3在上面一排，LED4~7在下面一排；左上角是LED0，右下角LED7
//	7-SEG Dispaly
	output [7:0] seven,
	output [0:3] seven_sel,	 //按实验箱的位序标识，DIGITAL0在最左边。为0时点亮对应位。
//  Address Bus
	output [20:0] mem_addr, // SRAM 18 bits; Flash memory 21 bits
//  Data Bus
	inout [15:0] mem_data, // SRAM 16 bits; Flash memory 8 bits
//	SRAM Interface
	output [1:0] sram_be,
	output sram_rd,
	output sram_wr,
	output sram_sel,
//  Flash Memory Interface
    output flash_oe,
    output flash_we,
    output flash_cs,
//	LCD Interface
	inout [7:0] lcd_data,
    output lcd_cs1,
    output lcd_cs2,
    output lcd_di,
    output lcd_e,
    output lcd_reset,
    output lcd_rw,
//	PS2 Interface
	output ps2_clk,
	output ps2_data,
	output ps2_2_clk,
	output ps2_2_data,
//  RS232 Interface
    input  rxd,
    output txd,
    input  rxd_2,
    output txd_2,
//  Motor Interface
    input  motor_counter,
    output motor_pwm,
//  DA Interface
    output da_a0,
    output da_a1,
    output [7:0] da_data,
    output da_ldac_n,
    output da_wr_n,
//  AD Interface
    output ad_convst_n,
    output ad_sclk,
    output ad_din,
    input  ad_dout,
    output ad_rfs,
    output ad_tfs,
//  USB Interface
    output [7:0] usb_addr,
    inout [15:0] usb_data,
    input usb_int,
    input usb_rdy,
    output usb_rst_n,
    output usb_cs_n,
    output usb_rd_n,
    output usb_wr_n

);

wire reset = ~reset_n;

assign	led = 8'b11111111; 		// 点亮所有指示灯
//assign	seven = 8'hFF;
//assign	seven_sel = 4'b0000; 	// 点亮所有数码管

//	SRAM 
assign mem_data = 16'hzzzz;
assign sel_sram = 1'b1;

//  Flash Memory
assign flash_cs = 1'b1;
assign flash_oe = 1'b1;

//	LCD
assign lcd_data = 8'hzz;

//  USB
assign usb_data = 16'hzzzz;

//实例化分频器
fenpin	fenpin_inst (
	.clock ( clkin ),
	.cout ( clk1 ),
	.q (  )
	);

//循环移位
wire [3:0] sel;
rlshifter rlshifter_sl(
      .clk(clk1),
      .reset(reset),
      .q(sel)
      );

//数码管低电平有效
assign seven_sel=~sel;

//8位计数器分频
fpcount fpcount_sl(
        .clk(clk1),
        .reset(reset),
        .clk_fp(clk2)
        );

//多路器
wire [3:0] muxout;
mux mux_sl(
      .select(sel),
      .in1(first),
      .in2(second),
      .in3(third),
      .in4(fouth),
      .out(muxout)
      );

//7段译码
decode4_7 decode4_7_sl(
      .seg(seven),
      .data(muxout)
      );
 
//16位计数
jscount jscount_sl(
         .reset(reset),
         .clk(clk2),
         .out1(first),
         .out2(second),
         .out3(third),
         .out4(fouth)
         );
endmodule