8count.v.bak

用VERILOG实现的秒表 用VERILOG实现的秒表

module 8count(clk,reset,cp)
  parameter width=8;
  input clk;
  input reset;
  output cp;
  reg cp;
  reg[width-1:0] cout;
  
 always@(posedge clk or posedge reset)
  begin 
   if(reset==1)
     count<=8'h00;
   else if(cout<128)
     begin
       cout<=cout+1;
       cp<=1;
     end
   else if(cout>127)
     begin
       cout<=cout+1;
       cp<=0;
     end
   else if(cout==8'hff)
     cout<=8'h00;
   end
endmodule