dpll_4count.txt

来自「这是基于verilog语言写的」· 文本 代码 · 共 19 行

module DPLL_4count(fout2,idout,N);
output fout2;
input  idout;
input[8:0] N;
reg fout2;
reg out3;

always @(posedge idout)
  begin
     if(out3==N)
        begin
           out3<=0;fout2<=1;
        end
     else if(out3!=N) 
        begin
           out3<=out3+1;fout2<=0;
        end
  end
endmodule