dpll_4count_tp.txt

来自「这是基于verilog语言写的」· 文本 代码 · 共 20 行

module DPLL_4count_tp;
reg idout,N;
wire fout2;

parameter dely=100;
DPLL_4count  inst_DPLL_4count_tp(fout2,idout,N);

initial
begin idout=1;N=2;
#(dely*20) N=3;
#(dely*20) N=6
#(dely*20)$stop;
end

always #(dely/2) idout=~idout;

initial
$monitor($time,,,"idout=%d,fout2=%d,N=%d", idout,fout2,N);
endmodule