dpll_h.v

来自「这是基于verilog语言写的」· Verilog 代码 · 共 25 行

module DPLL_H(idclock,kclock,H,reset);
output idclock;
input  kclock,reset;
input[7:0] H;
reg idclock;
reg[7:0] out;

always @(posedge kclock or negedge reset)
  begin
     if(reset==0)
       begin out<=0;idclock<=0; end
     else if (reset==1)
        begin
         if(out==(H-1))
            begin
               out<=0;idclock<=1;
            end

         else if(out!=(H-1)) 
            begin
              out<=out+1;idclock<=0;
            end
        end
  end
 endmodule