_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity IR_ShReg8 is
    port(
        Q1              : out    vl_logic_vector(31 downto 0);
        Q2              : out    vl_logic_vector(31 downto 0);
        D1              : in     vl_logic_vector(31 downto 0);
        D2              : in     vl_logic_vector(31 downto 0);
        flag            : in     vl_logic_vector(7 downto 0);
        snum            : in     vl_logic_vector(1 downto 0);
        clr             : in     vl_logic;
        clk             : in     vl_logic
    );
end IR_ShReg8;