_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 42 行

library verilog;
use verilog.vl_types.all;
entity CtrlUnit is
    port(
        IR1A            : in     vl_logic_vector(31 downto 0);
        IR1B            : in     vl_logic_vector(31 downto 0);
        IR2A            : in     vl_logic_vector(31 downto 0);
        IR2B            : in     vl_logic_vector(31 downto 0);
        IR3A            : in     vl_logic_vector(31 downto 0);
        IR3B            : in     vl_logic_vector(31 downto 0);
        ID1A            : in     vl_logic_vector(31 downto 0);
        ID1B            : in     vl_logic_vector(31 downto 0);
        ID2A            : in     vl_logic_vector(31 downto 0);
        ID2B            : in     vl_logic_vector(31 downto 0);
        ID3A            : in     vl_logic_vector(31 downto 0);
        ID3B            : in     vl_logic_vector(31 downto 0);
        NOP1A           : out    vl_logic;
        NOP1B           : out    vl_logic;
        NOP2A           : out    vl_logic;
        NOP2B           : out    vl_logic;
        NOP3A           : out    vl_logic;
        NOP3B           : out    vl_logic;
        En1A            : out    vl_logic;
        En1B            : out    vl_logic;
        En2A            : out    vl_logic;
        En2B            : out    vl_logic;
        En3A            : out    vl_logic;
        En3B            : out    vl_logic;
        Block1A         : in     vl_logic;
        Block1B         : in     vl_logic;
        MulBusy2A       : in     vl_logic;
        ToJmp2B         : in     vl_logic;
        OutSel2A        : out    vl_logic_vector(1 downto 0);
        OutSel2B        : out    vl_logic_vector(1 downto 0);
        MulLoad2A       : out    vl_logic;
        LdNewPc         : out    vl_logic;
        ReadA           : out    vl_logic;
        ReadB           : out    vl_logic;
        reset           : in     vl_logic
    );
end CtrlUnit;