_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity Logic32 is
    port(
        \out\           : out    vl_logic_vector(31 downto 0);
        a               : in     vl_logic_vector(31 downto 0);
        b               : in     vl_logic_vector(31 downto 0);
        op              : in     vl_logic_vector(1 downto 0)
    );
end Logic32;