_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity INS_DECODER is
    port(
        INS_OP          : in     vl_logic_vector(5 downto 0);
        ALU_OP          : out    vl_logic_vector(3 downto 0);
        ID              : out    vl_logic_vector(15 downto 0);
        RI              : out    vl_logic
    );
end INS_DECODER;