_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity \Block\ is
    port(
        blockA          : out    vl_logic;
        blockB          : out    vl_logic;
        ofAIR           : in     vl_logic_vector(31 downto 0);
        ofAID           : in     vl_logic_vector(22 downto 0);
        ofBIR           : in     vl_logic_vector(31 downto 0);
        ofBID           : in     vl_logic_vector(22 downto 0);
        exAIR           : in     vl_logic_vector(31 downto 0);
        exAID           : in     vl_logic_vector(22 downto 0);
        exBIR           : in     vl_logic_vector(31 downto 0);
        exBID           : in     vl_logic_vector(22 downto 0)
    );
end \Block\;