_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity IMME_EX is
    port(
        INSTR           : in     vl_logic_vector(31 downto 0);
        ID              : in     vl_logic_vector(15 downto 0);
        REG1            : in     vl_logic_vector(31 downto 0);
        IMME            : out    vl_logic_vector(31 downto 0)
    );
end IMME_EX;