_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity Adder16_M is
    port(
        sum             : out    vl_logic_vector(15 downto 0);
        cout            : out    vl_logic;
        P               : out    vl_logic;
        G               : out    vl_logic;
        a               : in     vl_logic_vector(15 downto 0);
        b               : in     vl_logic_vector(15 downto 0);
        cin             : in     vl_logic
    );
end Adder16_M;