_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity GET_OPER is
    port(
        FOR1            : in     vl_logic;
        FOR2            : in     vl_logic;
        RI              : in     vl_logic;
        REG1            : in     vl_logic_vector(31 downto 0);
        REG2            : in     vl_logic_vector(31 downto 0);
        IMME            : in     vl_logic_vector(31 downto 0);
        FORE1           : in     vl_logic_vector(31 downto 0);
        FORE2           : in     vl_logic_vector(31 downto 0);
        OPER1           : out    vl_logic_vector(31 downto 0);
        OPER2           : out    vl_logic_vector(31 downto 0)
    );
end GET_OPER;