_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity HardInt is
    port(
        IntExe          : out    vl_logic;
        IntType         : out    vl_logic_vector(7 downto 0);
        INTR            : in     vl_logic;
        INTRType        : in     vl_logic_vector(7 downto 0);
        IntClr          : in     vl_logic;
        IntEn           : in     vl_logic;
        clk             : in     vl_logic;
        reset           : in     vl_logic
    );
end HardInt;