_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity SYS_INS_DECODER is
    port(
        SysID           : out    vl_logic_vector(14 downto 0);
        SysIR           : in     vl_logic_vector(31 downto 0);
        preSysID        : in     vl_logic_vector(16 downto 0)
    );
end SYS_INS_DECODER;