_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity J_PATH is
    port(
        RI              : in     vl_logic;
        CLK             : in     vl_logic;
        CLR             : in     vl_logic;
        EN1             : in     vl_logic;
        PC              : in     vl_logic_vector(31 downto 0);
        OPER2           : in     vl_logic_vector(31 downto 0);
        J_ADDR          : out    vl_logic_vector(31 downto 0)
    );
end J_PATH;