_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity Ram is
    port(
        clk             : in     vl_logic;
        adr             : in     vl_logic_vector(31 downto 0);
        rami            : in     vl_logic_vector(31 downto 0);
        wren            : in     vl_logic;
        ramo            : out    vl_logic_vector(63 downto 0)
    );
end Ram;